[OmniOS-discuss] [developer] Re: [discuss] Trouble getting Supermicro board to see all its PCI-e slots

[Aakash Saini]

Hi Saso,
Please see reply within email.

 > prtpicl should display correctly details to resource addressing, cause
> > slots are assigned.
>
> Attached, both the short and verbose version.
>
I will check that.


>  >> ..."The problem appears to be that Illumos doesn't recognize any PCI
> > bridges beyond those attached to CPU1.
> >
> > yes, maybe its a PCIe-PCI bridging issue, even i doubt. try kdb debug
> > state...
> > ::bp pcieb`pcieb_attach
> > :c
> > pcieb`pcieb_dbg_print/W 0x1    --- this should display basic
> > debugged information
> > :c
>
> Compiled a debug version of the pcieb module and attached the output
> from this. Strangely enough, the output stopped for considerable time
> between lines 21 and 22 in the output, so between lines:
>
> pcieb(0): pwrINITCHILD: config regs setup for pci15d9,690 at 0
>
> and
>
> pcieb(1): pwrpcieb_pwr_disable: disabling PM



> after which lots of output proceeded quickly. Could it be that the
> probing code is getting stuck on and then giving up on probing a bridge
> here?
>

I don't know what system is doing.. if its PSM probing issue, could you
check it following
option edited/entered in file /etc/system and reboot.

set apix_enable = 0x0



>  > also. try with disabled (both) MSI and workaround patch to 41210/chipset
> > individually.
> > pcieb`pcieb_enable_msi/W 0x1
> > pcieb_disable_41210_wkarnd/W 0x1
>
> Neither setting changed anything.
>

sorry, my typing error. it should have been zero not one;
pcieb`pcieb_enable_msi/W 0x0



 > i'm not sure if there is any resource conflict issue; mdb -k |
> ::interrupts
> > as obviously, h/w is remote!
>
> Here's the output of that:
>
> # echo ::interrupts | mdb -k
> CPU/Vect  IRQ IPL Bus    Trg Type   Share APIC/INT# ISR
> 1/0x20    9   9   PCI    Lvl Fixed  1     0x0/0x9   acpi_wrapper_isr
> 2/0x20    11  14  PCI    Lvl Fixed  1     0x0/0xb   hpet_isr
> 3/0x20    -   7   PCI    Edg MSI    1     -         pcieb_intr_handler
> 4/0x20    -   5   PCI    Edg MSI-X  1     -         mrsas_isr
> 7/0x20    1   5   ISA    Edg Fixed  1     0x0/0x1   i8042_intr
> 8/0x20    12  5   ISA    Edg Fixed  1     0x0/0xc   i8042_intr
> 8/0x22    -   5   PCI    Edg MSI    1     -         mpt_intr
> 12/0x20   3   12  ISA    Edg Fixed  1     0x0/0x3   asyintr
> 13/0x20   -   4   PCI    Edg MSI    1     -         pcieb_intr_handler
> 14/0x20   -   7   PCI    Edg MSI    1     -         pcieb_intr_handler
> 15/0x20   -   4   PCI    Edg MSI    1     -         pcieb_intr_handler
> 16/0x20   -   7   PCI    Edg MSI    1     -         pcieb_intr_handler
> 17/0x20   -   4   PCI    Edg MSI    1     -         pcieb_intr_handler
> 18/0x20   16  9   PCI    Lvl Fixed  1     0x0/0x10  ehci_intr
> 19/0x20   23  9   PCI    Lvl Fixed  1     0x0/0x17  ehci_intr
> 20/0x20   -   6   PCI    Edg MSI-X  1     -         igb_intr_tx_other
> 21/0x20   -   6   PCI    Edg MSI-X  1     -         igb_intr_rx
> all/0xf0  -   15  -      Edg IPI    1     -         xc_serv
> all/0xf1  -   11  -      Edg IPI    0     -         poke_cpu
> all/0xf2  -   14  -      Edg IPI    1     -         kcpc_hw_overflow_intr
> all/0xf3  -   15  -      Edg IPI    1     -         apic_error_intr
> all/0xf4  -   2   -      Edg IPI    1     -         cmi_cmci_trap
> all/0xf5  -   14  -      Edg IPI    1     -         cbe_fire
> all/0xf6  -   14  -      Edg IPI    1     -         cbe_fire
>
> Hope this provides more insight. If it helps, I can arrange for direct
> access to the machine (both to the OS and the BMC).
>

handlers look ok here... let see if things workout with basic options,
else would require access to h/w.

Cheers,




> Cheers,
> --
> Saso
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://omniosce.org/ml-archive/attachments/20130501/f770e0c2/attachment.html>